Routing congestion analysis and reduction in deep sub-micron VLSI design

摘要

Congestion is one of the main optimization objectives in global routing. However, the optimization performance is constrained because the cells are already fixed at this stage. Therefore, designer can save substantial time and resources by detecting and reducing congested regions during the planning stages. An efficient and yet accurate congestion estimation model is crucial to be included in the inner loop of floorplanning and placement design. In this dissertation, we mainly focus on routing congestion modeling and reduction during floorplanning and placement.